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(R)
LCP1521S/LCP152DEE
PROGRAMMABLE TRANSIENT VOLTAGE SUPPRESSOR FOR SLIC PROTECTION
ASD
(Application Specific Devices)
FEATURES Dual programmable transient suppressor Wide negative firing voltage range: VMGL = -150 V max.

Low dynamic switching voltages: VFP and VDGL Low gate triggering current: IGT = 5 mA max Peak pulse current: IPP = 30 A (10/1000 s) Holding current: IH = 150 mA min Low space consuming package Table 1: Order Codes Part Number LCP1521S LCP1521SRL LCP152DEERL Marking CP152S CP152S LCP SO-8 LCP1521S QFN 3x3 6 Leads LCP152DEE
DESCRIPTION These devices have been especially designed to protect new high voltage, as well as classical SLICs, against transient overvoltages. Positive overvoltages are clamped by 2 diodes. Negative surges are suppressed by 2 thyristors, their breakdown voltage being referenced to -VBAT through the gate. These components present a very low gate triggering current (IGT) in order to reduce the current consumption on printed circuit board during the firing phase. BENEFITS TRISILsTM are not subject to ageing and provide a fail safe mode in short circuit for a better protection. Trisils are used to help equipment to meet various standards such as UL60950, IEC950 / CSA C22.2, UL1459 and FCC part68. Trisils have UL94 V0 resin approved (Trisils are UL497B approved [file: E136224]).
Figure 1: LCP1521S Functional Diagram
TIP
1
TIP
GATE
GND
NC
GND
RING
RING
Figure 2: LCP152DEE Functional Diagram
TIP
TIP
GATE
GND
NC
RING
RING
TM: TRISIL is a trademark of STMicroelectronics.
May 2005
REV. 4
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LCP1521S/LCP152DEE
Table 2: Compliances with the following Standards STANDARD GR-1089 Core First level GR-1089 Core Second level GR-1089 Core Intra-building ITU-T-K20/K21 ITU-T-K20 (IEC61000-4-2) VDE0433 VDE0878 IEC61000-4-5 FCC Part 68, lightning surge type A FCC Part 68, lightning surge type B Table 3: Thermal Resistances Symbol Rth(j-a) Parameter Junction to ambient SO-8 QFN Value 120 140 Unit C/W Peak Surge Voltage (V) 2500 1000 5000 1500 6000 1500 8000 15000 4000 2000 4000 2000 4000 4000 1500 800 1000 Voltage Waveform 2/10s 10/1000s 2/10s 2/10s 10/700s 1-60ns 10/700s 1.2/50s 10/700s 1.2/50s 10/160s 10/560s 9/720s Required peak current (A) 500 100 500 100 150 37.5 Current Waveform 2/10s 10/1000s 2/10s 2/10s 5/310s Minimum serial resistor to meet standard () 12 24 24 0 110 0 0 0 60 10 0 0 60 0 22.5 15 0
ESD contact discharge ESD air discharge 100 50 100 50 100 100 200 100 25 5/310s 1/20s 5/310s 8/20s 10/160s 10/560s 5/320s
Table 4: Electrical Characteristics (Tamb = 25C) Symbol IGT IH IRM IRG VRM VGT VF VFP VDGL VRG C
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Parameter Gate triggering current Holding current Reverse leakage current LINE / GND Reverse leakage current GATE / LINE Reverse voltage LINE / GND
VR VRM
I
Gate triggering voltage Forward drop voltage LINE / GND Peak forward voltage LINE / GND Dynamic switching voltage GATE / LINE Reverse voltage GATE / LINE Capacitance LINE / GND
VF IRM IR IH
V
IPP
LCP1521S/LCP152DEE
Table 5: Absolute Ratings (Tamb = 25C, unless otherwise specified) Symbol Parameter 10/1000s 8/20s 10/560s 5/310s 10/160s 1/20s 2/10s t = 20ms t = 200ms t = 1s t = 10ms -40C < Tamb < +85C -40C < Tamb < +85C Value 30 100 35 40 50 100 150 12 6 4.5 2 -150 -150 -55 to +150 150 260 Unit
IPP
Peak pulse current
A
ITSM IGSM VMLG VMGL Tstg Tj TL
Non repetitive surge peak on-state current (50Hz sinusoidal) Maximum gate current (50Hz sinusoidal) Maximum voltage LINE/GND Maximum voltage GATE/LINE Storage temperature range Maximum junction temperature
A A V C C
Maximum lead temperature for soldering during 10 s.
Table 6: Repetitive peak pulse current Symbol tr tp Definition Rise time (s) Pulse duration (s) Example Pulse waveform 10/1000s: tr = 10s tp = 1000s
% IPP
100 50 0 tr tp
t
Table 7: Parameters related to the diode LINE / GND (Tamb = 25C) Symbol VF VFP (note 1) IF = 5A 10/700s 1.2/50s 2/10s 1.5kV 1.5kV 2.5kV Test conditions t = 500s RS = 10 RS = 10 RS = 62 Max 3 5 9 30 Unit V V
Note 1: see test circuit for VFP; RS is the protection resistor located on the line card.
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LCP1521S/LCP152DEE
Table 8: Parameters related to the protection Thyristors (Tamb = 25C, unless otherwise specified) Symbol IGT IH VGT IRG VDGL VGND / LINE = -48V VGATE = -48V (note 2) at IGT VRG = -150V VRG = -150V VGATE = -48V (note 3) 10/700s 1.2/50s 2/10s 1.5kV 1.5kV 2.5kV RS = 10 RS = 10 RS = 62 IPP = 30A IPP = 30A IPP = 38A 7 10 25 V Tj = 25C Tj = 85C Test conditions Typ 0.1 150 2.5 5 50 Max 5 Unit mA mA V A
Note 2: see functional holding current (IH) test circuit Note 3: see test circuit for VDG The oscillations with a time duration lower than 50ns are not taken into account.
Table 9: Parameters related to diode and protection Thyristors (Tamb = 25C, unless otherwise specified) Symbol IRM C VGATE / LINE = -1V VGATE / LINE = -1V Test conditions VRM = -150V VRM = -150V Tj = 25C Tj = 85C 15 35 Typ Max 5 50 Unit A pF
VR = 50V bias, VRMS = 1V, F = 1MHz VR = 2V bias, VRMS = 1V, F = 1MHz
Figure 3: Functional Holding Current (IH) test circuit: GO-NO GO test
R
Surge generator
VBAT = - 100V
D.U.T
This is a GO-NO GO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE: - Adjust the current level at the IH value by short circuiting the D.U.T. - Fire the D.U.T. with a surge current: IPP = 10A, 10/1000s - The D.U.T. will come back to the off-state within a duration of 50ms max.
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LCP1521S/LCP152DEE
Figure 4: Test circuit for VFP and VDGL parameters
(V is defined in unload condition)
P
R4 TIP R2 RING R3
L
VP
C1
R1
C2
G ND
Pulse (s) tr tp 10 1.2 2 700 50 10
Vp (V) 1500 1500 2500
C1 (F) 20 1 10
C2
(nF)
L (H) 0 0 1.1
R1
()
R2
()
R3
()
R4
()
IPP
(A)
Rs
()
200 33 0
50 76 1.3
15 13 0
25 25 3
25 25 3
30 30 38
10 10 62
TECHNICAL INFORMATION Figure 5: LCP152 concept behavior
Rs1
L1
TIP IG ID1 T1 Gate Th1 D1 GND
V Tip
GND
-Vbat
C
Rs2
RING
VRing
L2
Figure 5 shows the classical protection circuit using the LCP152 crowbar concept. This topology has been developed to protect the new high voltage SLICs. It allows to program the negative firing threshold while the positive clamping value is fixed at GND. When a negative surge occurs on one wire (L1 for example) a current IG flows through the base of the transistor T1 and then injects a current in the gate of the thyristor Th1. Th1 fires and all the surge current flows through the ground. After the surge when the current flowing through Th1 becomes less negative than the holding current IH, then Th1 switches off. When a positive surge occurs on one wire (L1 for example) the diode D1 conducts and the surge current flows through the ground.
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LCP1521S/LCP152DEE
Figure 6: Example of PCB layout based on LCP152 protection
LCP1521S
220 nF
To line side
GND
To SLIC side
Figure 6 shows the classical PCB layout used to optimize line protection. The capacitor C is used to speed up the crowbar structure firing during the fast surge edges. This allows to minimize the dynamical breakover voltage at the SLIC Tip and Ring inputs during fast strikes. Note that this capacitor is generally present around the SLIC - Vbat pin. So to be efficient it has to be as close as possible from the LCP152 Gate pin and from the reference ground track (or plan) (see figure 6). The optimized value for C is 220nF. The series resitors Rs1 and Rs2 designed in figure 5 represent the fuse resistors or the PTC which are mandatory to withstand the power contact or the power induction tests imposed by the various country standards. Taking into account this fact the actual lightning surge current flowing through the LCP is equal to: I surge = V surge / (Rg + Rs) With V surge = peak surge voltage imposed by the standard. Rg = series resistor of the surge generator Rs = series resistor of the line card (e.g. PTC)
e.g. For a line card with 30 of series resistors which has to be qualified under GR1089 Core 1000V 10/1000s surge, the actual current through the LCP152 is equal to: I surge = 1000 / (10 + 30) = 25A The LCP152 is particularly optimized for the new telecom applications such as the fiber in the loop, the WLL, the remote central office. In this case, the operating voltages are smaller than in the classical system. This makes the high voltage SLICs particularly suitable. The schematics of figure 7 on next page gives the most frequent topology used for these applications.
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LCP1521S/LCP152DEE
Figure 7: Protection of high voltage SLIC
-Vbat Rs (*) TIP Gate TIP GND GND RING Rs (*) RING
Line
GND
220nF
SLIC
LCP152xx Line card
Rs (*) = PTC or fuse resistor
Figure 8: Surge peak current versus overload duration
ITSM(A)
14 12 10
F=50Hz Tj initial=25C
Figure 9: Relative variation of holding current versus junction temperature
IH[Tj] / IH[Tj=25C]
1.3 1.2 1.1
8
1
6
0.9
4 2
0.8
t(s)
0 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03
Tj(C)
0.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
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LCP1521S/LCP152DEE
Figure 10: SO-8 Package Mechanical Data DIMENSIONS Millimeters Inches Min.
ddd C
A2 A C (Seating Plane) h x 45 0.25mm (Gage Plane)
REF. A A1 A2 B C D E e H h L k ddd
Max.
Min.
Max.
B
e
A1
k
L
D
8
5
E
H
1
4
1.35 1.75 0.053 0.069 0.1 0.25 0.004 0.010 1.10 1.65 0.043 0.065 0.33 0.51 0.013 0.020 0.19 0.25 0.007 0.010 4.80 5.00 0.189 0.197 3.80 4.00 0.150 0.157 1.27 Typ. 0.05 Typ. 5.80 6.20 0.228 0.244 0.25 0.50 0.010 0.019 0.40 1.27 0.016 0.050 8 (max) 0.100 0.004
Figure 11: Foot Print Dimensions (in millimeters)
6.8 0.6 4.2
1.27
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LCP1521S/LCP152DEE
Figure 12: QFN 3x3 S Leads Package Mechanical Data DIMENSIONS Millimeters Inches Min. A A1 A2 A3 b D D2 E E2 e L L1 L2 K < 0.80 0 0.65 20 0.33 2.90 1.92 2.90 1.11 0.20 0.24 0.20 0 3 3 0.95
Typ. Max. Min. Typ. Max.
REF.
1 0.031 0.05 0 0.75 0.026 0.43 3.10 2.12 3.10 1.31
0.040 0.002 0.030
0.787 0.013 0.017 0.114 0.118 0.122 0.076 0.083 0.114 0.118 0.122 0.044 0.051 0.037 0.45 0.008 0.018 0.009 0.13 0.005 0.008 12 0 12
Figure 13: Foot Print Dimensions (in millimeters)
0.95 0.48
1.05 0.35 0.34 1.21
2.02 4.00
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LCP1521S/LCP152DEE
Table 10: Ordering Information Part Number LCP1521S LCP1521SRL LCP152DEERL Marking CP152S CP152S LCP Package SO-8 QFN 3x3 6L Weight 0.08 g 0.022 g Base qty 100 2500 3000 Delivery mode Tube Tape & reel Tape & reel
Table 11: Resision History Date Sep-2003 08-Dec-2004 17-Feb-2005 03-May-2005 Revision 1A 2 3 4 First issue. 1/ Page 2 table 3: Thermal resistances changed from 130C/W (SO-8) to 120 C/W and from 170 C/W (QFN) to 140C/W. 2/ SO-8 and QFN footprint dimensions added. Table 9 on page 4: correction of typo on capacitance unit. Table 5 on page 3: ITSM value @ t= 1s from 4A to 4.5A. Description of Changes
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LCP1521S/LCP152DEE
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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